Implementation of encoder and decoder for LDPC codes based on FPGA

doi:10.21629/JSEE.2019.04.02

Journal of Systems Engineering and Electronics ›› 2019, Vol. 30 ›› Issue (4): 642-650.doi: 10.21629/JSEE.2019.04.02

• Electronics Technology • Previous Articles Next Articles

Implementation of encoder and decoder for LDPC codes based on FPGA

Kun CHENG¹(), Qi SHEN^2,³(), Shengkai LIAO^2,^3,*(), Chengzhi PENG^2,³()

¹ Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China
² Shanghai Branch, National Laboratory for Physical Sciences at Microscale and Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China
³ Chinese Academy of Sciences Center for Excellence and Synergetic Innovation Center in Quantum Information and Quantum Physics, University of Science and Technology of China, Shanghai 201315, China

Received:2018-12-13 Online:2019-08-01 Published:2019-08-29
Contact: Shengkai LIAO E-mail:chengkun@live.cn;shenqi@ustc.edu.cn;skliao@ustc.edu.cn;pcz@ustc.edu.cn
About author:CHENG Kun was born in 1984. He received his master's degree in Department of Free Electronic Laser from Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Shanghai, China, in 2011. He is currently working toward his Ph.D. degree in quantum key distribution at the University of Science and Technology of China, Hefei, China. E-mail: chengkun@live.cn|SHEN Qi was born in 1986. He received his Ph.D. degree in Department of Modern Physics from University of Science and Technology of China, Hefei, China, in 2013. He has been with National Laboratory for Physical Sciences at Microscale and Department of Modern Physics, University of Science and Technology of China, and Chinese Academy of Sciences Center for Excellence and Synergetic Innovation Center in Quantum Information and Quantum Physics, University of Science and Technology of China, as an assistant researcher. His research interests include quantum key distribution, and time-to-digital converter. E-mail: shenqi@ustc.edu.cn|LIAO Shengkai was born in 1983. He received his Ph.D. degree in Shanghai Institute of Technology, Chinese Academy of Sciences, Shanghai, China, in 2010. Since 2010, He has been with National Laboratory for Physical Sciences at Microscale and Department of Modern Physics, University of Science and Technology of China, and Chinese Academy of Sciences Center for Excellence and Synergetic Innovation Center in Quantum Information and Quantum Physics, University of Science and Technology of China, as a professor researcher. His research interests include light source, transmission channel, and detection of quantum key distribution. E-mail: skliao@ustc.edu.cn|PENG Chengzhi was born in 1976. He received his Ph.D. degree in Department of Modern Physics from University of Science and Technology of China, Hefei, China, in 2005. From 2007 to 2009 he was with Tsinghua University as an assistant professor. Since 2009, He has been with National Laboratory for Physical Sciences at Microscale and Department of Modern Physics, University of Science and Technology of China, and Chinese Academy of Sciences Center for Excellence and Synergetic Innovation Center in Quantum Information and Quantum Physics, University of Science and Technology of China, as a professor researcher. His research interests include light source, transmission channel, and detection of quantum key distribution. E-mail: pcz@ustc.edu.cn
Supported by:
the National Natural Science Foundation of China(11705191);the Anhui Provincial Natural Science Foundation(1808085QF180);the Natural Science Foundation of Shanghai(18ZR1443600);This work was supported by the National Natural Science Foundation of China (11705191), the Anhui Provincial Natural Science Foundation (1808085QF180), and the Natural Science Foundation of Shanghai (18ZR1443600)

Abstract

Abstract:

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check (IR-QC-LDPC) codes, with a dual-diagonal parity structure. A normalized min-sum algorithm (NMSA) is employed for decoding. The whole verification of the encoding and decoding algorithm is simulated with Matlab, and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6% and 1.04%. Based on the results of simulation, multi-code rates are compatible with different basis matrices. Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array (FPGA). The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6% are realized based on FPGA.

Key words: low-density parity-check (LDPC), field programmable gate array (FPGA), normalized min-sum algorithm (NMSA)

Kun CHENG, Qi SHEN, Shengkai LIAO, Chengzhi PENG. Implementation of encoder and decoder for LDPC codes based on FPGA[J]. Journal of Systems Engineering and Electronics, 2019, 30(4): 642-650.

Figures/Tables 12

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References 36

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Module	LUT	FF
key_source	195	464
ldpc_encode	2 383	4 521
iter_control	22	16
data_load	1 042	1 969
vnu_process	5 966	7 157
cnu_process	38 159	15 347
decode_judge	16 897	3 966
addr_convt	5 840	0

Resource	Utilization	Availability	Ratio%
LUT	102 622	242 400	42.34
LUTRAM	3 287	112 800	2.91
FF	49 909	484 800	10.29
BRAM	210	600	35

Implementation of encoder and decoder for LDPC codes based on FPGA

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